EnggVizLab
module.v
SYSTEM CONSOLE
// EnggViz Silicon Lab — ready.
// Load an example or write HDL to begin.
100%

No waveform yet — run Simulate.

100%

No schematic yet — run RTL.

Resource Report

Wires
Cells
Flip-Flops

Board Constraint Generator

Map RTL ports → physical FPGA pins

Load a module to map pins.

READY
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module.v
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1 line
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Ctrl+Enter simulate   Ctrl+H find
EnggViz Silicon Lab v2.1